The conventional testing method for detecting a fault of a digital circuit is based on logic testing, in which the output logic values of a circuit under test are observed. Such a conventional testing method as described above is incapable of detecting an intermediate fault of the CMOS circuit at such time when the output voltage value is intermediate between V.sub.DD (logic 1) and GND (logic 0).
According to a technical proposal disclosed by C. F. Hawkins, et al in their research paper entitled "Quiescent Power Supply Current Measurement for CMOS IC Defect Detection" and published in the May, 1989 issue of IEEE Trans. on Industrial Electronics, such an intermediate fault as described above can be defected by the I.sub.DDQ current testing method, which is used in conjunction with some automatic testing equipment (ATE) or built-in current sensors (BICS). However, the employment of automatic testing equipment can result in a substantial reduction in the testing speed and the sensing resolution of the measurable current. On the other hand, the employment of the built-in current sensors can undermine seriously the performance of the circuit under test unless the expensive BiCMOS or dual power supply technique is used. Moreover, the task of designing the CMOS circuits must be carried out in accordance with a specific set of designing rules so as to enable the CMOS circuits to be tested for an intermediate fault by the I.sub.DDQ testing method. It must be noted here that the specific set of designing rules is implemented at the expense of the design feasibility of the CMOS circuits.
Another method for testing the intermediate voltage fault was disclosed by G. G. Freeman, et al in their research paper entitled "Two CMOS Metastability Sensors" and published in the 1986 Proceedings of the International Test Conference. This method is based on the theory that the metastability brings about intermediate voltages, which can be therefore detected by the metastability sensors. However, the implementation of the metastability method calls for the employment of a number of complementary input signals. As a result, the metastability method can undermine seriously the performance of the circuit under test.